View UC3844_1867610.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2006 july, 2006 ? rev. 7 1 publication order number: UC3844/d UC3844, uc3845, uc2844, uc2845 high performance current mode controllers the UC3844, uc3845 series are high performance fixed frequency current mode controllers. they are specifically designed for off ? line and dc ? to ? dc converter applications offering the designer a cost effective solution with minimal external components. these integrated circuits feature an oscillator, a te mperature compensated reference, high gain error amplifier, current sens ing comparator, and a high current totem pole output ideally suited for driving a power mosfet. also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle ? by ? cycle current limiting, a latch for single pulse metering, and a flip ? flop which blanks the output off every other oscillator cycle, allowing output dead times to be programmed for 50% to 70%. these devices are available in an 8 ? pin dual ? in ? line plastic package as well as the 14 ? pin plastic surface mount (soic ? 14). the soic ? 14 package has separate power and ground pins for the totem pole output stage. the ucx844 has uvlo thresholds of 16 v (on) and 10 v (off), ideally suited for off ? line converters. the ucx845 is tailored for lower voltage applications having uvlo thresholds of 8.5 v (on) and 7.6 v (off). features ? current mode operation to 500 khz output switching frequency ? output deadtime adjustable from 50% to 70% ? automatic feed forward compensation ? latching pwm for cycle ? by ? cycle current limiting ? internally trimmed reference with undervoltage lockout ? high current totem pole output ? input undervoltage lockout with hysteresis ? low startup and operating current ? direct interface with on semiconductor sensefet products ? pb ? free packages are available figure 1. simplified block diagram 5.0v reference flip flop & latching pwm v cc undervoltage lockout oscillator error amplifier 7(12) v c 7(11) output 6(10) pwr gnd 5(8) 3(5) current sense v ref 8(14) 4(7) 2(3) 1(1) gnd 5(9) r t c t voltage feedback r r + ? v ref undervoltage lockout output comp. pin numbers in parenthesis are for the d suffix soic ? 14 package. v cc 14 soic ? 14 d suffix case 751a 1 1 8 pdip ? 8 n suffix case 626 pin connections (top view) v ref (top view) compensation voltage feedback current sense r t /c t v ref v cc output gnd 1 2 3 45 6 7 8 compensation nc voltage feedback nc current sense nc r t /c t nc v cc v c output gnd power ground 1 2 3 4 5 6 7 9 8 10 11 12 13 14 see detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. ordering information see general marking information in the device marking section on page page 14 of this data sheet. device marking information 1 8 soic ? 8 d1 suffix case 751a http://onsemi.com
UC3844, uc3845, uc2844, uc2845 http://onsemi.com 2 maximum ratings rating symbol value unit total power supply and zener current (i cc + i z ) 30 ma output current, source or sink (note 1) i o 1.0 a output energy (capacitive load per cycle) w 5.0 j current sense and voltage feedback inputs v in ? 0.3 to + 5.5 v error amp output sink current i o 10 ma power dissipation and thermal characteristics d suffix, plastic package, case 751a maximum power dissipation @ t a = 25 c thermal resistance junction ? to ? air n suffix, plastic package, case 626 maximum power dissipation @ t a = 25 c thermal resistance junction ? to ? air p d r ja p d r ja 862 145 1.25 100 mw c/w w c/w operating junction temperature t j + 150 c operating ambient temperature UC3844, uc3845 uc2844, uc2845 t a 0 to + 70 ? 25 to + 85 c storage temperature range t stg ? 65 to + 150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. maximum package power dissipation limits must be observed. electrical characteristics (v cc = 15 v, (note 2), r t = 10 k, c t = 3.3 nf, t a = t low to t high (note 3), unless otherwise noted.) uc284x uc384x characteristics symbol min typ max min typ max unit reference section reference output voltage (i o = 1.0 ma, t j = 25 c) v ref 4.95 5.0 5.05 4.9 5.0 5.1 v line regulation (v cc = 12 v to 25 v) reg line ? 2.0 20 ? 2.0 20 mv load regulation (i o = 1.0 ma to 20 ma) reg load ? 3.0 25 ? 3.0 25 mv temperature stability t s ? 0.2 ? ? 0.2 ? mv/ c total output variation over line, load, temperature v ref 4.9 ? 5.1 4.82 ? 5.18 v output noise voltage (f = 10 hz to khz, t j = 25 c) v n ? 50 ? ? 50 ? v long term stability (t a = 125 c for 1000 hours) s ? 5.0 ? ? 5.0 ? mv output short circuit current i sc ? 30 ? 85 ? 180 ? 30 ? 85 ? 180 ma oscillator section frequency t j = 25 c t a = t low to t high f osc 47 46 52 ? 57 60 47 46 52 ? 57 60 khz frequency change with voltage (v cc = 12 v to 25 v) f osc/ v ? 0.2 1.0 ? 0.2 1.0 % frequency change with temperature t a = t low to t high f osc/ t ? 5.0 ? ? 5.0 ? % oscillator voltage swing (peak ? to ? peak) v osc ? 1.6 ? ? 1.6 ? v discharge current (v osc = 2.0 v, t j = 25 c) i dischg ? 10.8 ? ? 10.8 ? ma error amplifier section voltage feedback input (v o = 2.5 v) v fb 2.45 2.5 2.55 2.42 2.5 2.58 v input bias current (v fb = 2.7 v) i ib ? ? 0.1 ? 1.0 ? ? 0.1 ? 2.0 a open loop voltage gain (v o = 2.0 v to 4.0 v) a vol 65 90 ? 65 90 ? db 2. adjust v cc above the startup threshold before setting to 15 v. 3. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. t low =0 c for UC3844, uc3845 t high = +70 c for UC3844, uc3845 ? 25 c for uc2844, uc2845 +85 c for uc2844, uc2845
UC3844, uc3845, uc2844, uc2845 http://onsemi.com 3 electrical characteristics (v cc = 15 v, (note 4), r t = 10 k, c t = 3.3 nf, t a = t low to t high (note 5), unless otherwise noted.) uc284x uc384x characteristics symbol min typ max min typ max unit error amplifier section (continued) unity gain bandwidth (t j = 25 c) bw 0.7 1.0 ? 0.7 1.0 ? mhz power supply rejection ratio (v cc = 12 v to 25 v) psrr 60 70 ? 60 70 ? db output current sink (v o = 1.1 v, v fb = 2.7 v) source (v o = 5.0 v, v fb = 2.3 v) i sink i source 2.0 ? 0.5 12 ? 1.0 ? ? 2.0 ? 0.5 12 ? 1.0 ? ? ma output voltage swing high state (r l = 15 k to ground, v fb = 2.3 v) low state (r l = 15 k to v ref , v fb = 2.7 v) v oh v ol 5.0 ? 6.2 0.8 ? 1.1 5.0 ? 6.2 0.8 ? 1.1 v current sense section current sense input voltage gain (notes 6 & 7) a v 2.85 3.0 3.15 2.85 3.0 3.15 v/v maximum current sense input threshold (note 6) v th 0.9 1.0 1.1 0.9 1.0 1.1 v power supply rejection ratio v cc = 12 v to 25 v (note 6) psrr ? 70 ? ? 70 ? db input bias current i ib ? ? 2.0 ? 10 ? ? 2.0 ? 10 a propagation delay (current sense input to output) t plh(in/out) ? 150 300 ? 150 300 ns output section output voltage low state (i sink = 20 ma) (i sink = 200 ma) high state (i sink = 20 ma) (i sink = 200 ma) v ol v oh ? ? 12 12 0.1 1.6 13.5 13.4 0.4 2.2 ? ? ? ? 13 12 0.1 1.6 13.5 13.4 0.4 2.2 ? ? v output voltage with uvlo activated v cc = 6.0 v, i sink = 1.0 ma v ol(uvlo) ? 0.1 1.1 ? 0.1 1.1 v output voltage rise time (c l = 1.0 nf, t j = 25 c) t r ? 50 150 ? 50 150 ns output voltage fall time (c l = 1.0 nf, t j = 25 c) t f ? 50 150 ? 50 150 ns undervoltage lockout section startup threshold ucx844 ucx845 v th 15 7.8 16 8.4 17 9.0 14.5 7.8 16 8.4 17.5 9.0 v minimum operating voltage after turn ? on ucx844 ucx845 v cc(min) 9.0 7.0 10 7.6 11 8.2 8.5 7.0 10 7.6 11.5 8.2 v pwm section duty cycle maximum minimum dc max dc min 46 ? 48 ? 50 0 47 ? 48 ? 50 0 % total device power supply current (note 4) startup: (v cc = 6.5 v for ucx845a, (v cc 14 v for ucx844) operating i cc ? ? 0.5 12 1.0 17 ? ? 0.5 12 1.0 17 ma power supply zener voltage (i cc = 25 ma) v z 30 36 ? 30 36 ? v 4. adjust v cc above the startup threshold before setting to 15 v. 5. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. t low =0 c for UC3844, uc3845 t high = +70 c for UC3844, uc3845 ? 25 c for uc2844, uc2845 +85 c for uc2844, uc2845 6. this parameter is measured at the latch trip point with v fb = 0 v. 7. comparator gain is defined as: a v v output compensation v current sense input
UC3844, uc3845, uc2844, uc2845 http://onsemi.com 4 0 v o , error amp output voltage (v) 0 , current sense input threshold (v) v th 0.2 0.4 0.6 0.8 1.0 1.2 2.0 4.0 6.0 8.0 v cc = 15 v t a = 25 c t a = ?55 c t a = 125 c r t , timing resistor (k ) figure 2. timing resistor versus oscillator frequency figure 3. output deadtime versus oscillator frequency figure 4. error amp small signal transient response figure 5. error amp large signal transient response 0.5 s/div 20 mv/div v cc = 15 v a v = ?1.0 t a = 25 c v cc = 15 v a v = ?1.0 t a = 25 c 1.0 s/div 200 mv/div 10 k 20 k 50 k 100 k 200 k 500 k 1.0 m f osc , oscillator frequency (hz) v cc = 15 v t a = 25 c 10 k 20 k 50 k 100 k 200 k 500 k 1.0 m f osc , oscillator frequency (hz) % dt, percent output deadtime figure 6. error amp open loop gain and phase versus frequency figure 7. current sense input threshold versus error amp output voltage note: output switches at one?half the oscillator frequency. c t = 10 nf 5.0 nf 2.0 nf 1.0 nf 100 pf 500 pf 200 pf 2.55 v 2.5 v 2.45 v 2.5 v 3.0 v 2.0 v 10 0 50 20 10 5.0 2.0 1.0 75 70 65 60 55 50 ?20 a vol , open loop voltage gain (db) 10 m 10 f, frequency (hz) gain phase v cc = 15 v v o = 2.0 v to 4.0 v r l = 100 k t a = 25 c 0 30 60 90 120 150 180 100 1.0 k 10 k 100 k 1.0 m 0 20 40 60 80 100 , excess phase (degrees)
UC3844, uc3845, uc2844, uc2845 http://onsemi.com 5 figure 8. reference voltage change versus source current figure 9. reference short circuit current versus temperature figure 10. reference load regulation figure 11. reference line regulation , output voltage change (2.0 mv/div) o 2.0 ms/div v , output voltage change (2.0 mv/div) o 2.0 ms/div v v cc = 12 v to 25 v t a = 25 c , reference voltage change (mv) ref 0 20 40 60 80 100 120 i ref , reference source current (ma) v v cc = 15 v t a = ?55 c t a = 25 c t a = 125 c , reference short circuit current (ma) sc ?55 ?25 0 25 50 75 100 125 t a , ambient temperature ( c) v cc = 15 v r l 0.1 i figure 12. output saturation voltage versus load current figure 13. output waveform 50 ns/div v cc = 15 v c l = 1.0 nf t a = 25 c 800 600 400 200 0 i o , output load current (ma) , output saturation voltage (v) sat v v cc t a = 25 c t a = ?55 c sink saturation (load to v cc ) gn d source saturation (load to ground) t a = ?55 c v cc = 15 v 80 s pulsed load 120 hz rate t a = 25 c v cc = 15 v i o = 1.0 ma to 20 ma t a = 25 c 0 ?4.0 ?8.0 ?12 ?16 ?20 ?24 110 90 70 50 90% 10% 0 1.0 2.0 3.0 ?2.0 ?1.0 0
UC3844, uc3845, uc2844, uc2845 http://onsemi.com 6 i cc , supply current figure 14. output cross conduction figure 15. supply current versus supply voltage 100 ns/div v cc = 30 v c l = 15 pf t a = 255c 100 ma/div 20 v/div 25 20 15 10 5 0 010203040 v cc , supply voltage (v) r t = 10 k c t = 3.3 nf v fb = 0 v i sense = 0 v t a = 255c ucx845 ucx844 v cc , output voltage i cc , supply current (ma) pin function description pin function description 8 ? pin 14 ? pin 1 1 compensation this pin is error amplifier output and is made available for loop compensation. 2 3 voltage feedback this is the inverting input of the error amplifier. it is normally connected to the switching power supply output through a resistor divider. 3 5 current sense a voltage proportional to inductor current is connected to this input. the pwm uses this information to terminate the output switch conduction. 4 7 r t /c t the oscillator frequency and maximum output duty cycle are programmed by connecting resistor r t to v ref and capacitor c t to ground. operation to 1.0 mhz is possible. 5 ? gnd this pin is combined control circuitry and power ground (8 ? pin package only). 6 10 output this output directly drives the gate of a power mosfet. peak currents up to 1.0 a are sourced and sunk by this pin. the output switches at one ? half the oscillator frequency. 7 12 v cc this pin is the positive supply of the control ic. 8 14 v ref this is the reference output. it provides charging current for capacitor c t through resistor r t . ? 8 power ground this pin is a separate power ground return (14 ? pin package only) that is connected back to the power source. it is used to reduce the effects of switching transient noise on the control circuitry. ? 11 v c the output high state (v oh ) is set by the voltage applied to this pin (14 ? pin package only). with a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry. ? 9 gnd this pin is the control circuitry ground return (14 ? pin package only) and is connected to back to the power source ground. ? 2,4,6,13 nc no connection (14 ? pin package only). these pins are not internally connected.
UC3844, uc3845, uc2844, uc2845 http://onsemi.com 7 operating description the UC3844, uc3845 series are high performance, fixed frequency, current mode controllers. they are specifically designed for off ? line and dc ? to ? dc converter applications offering the designer a cost effective solution with minimal external components. a representative block diagram is shown in figure 16. oscillator the oscillator frequency is programmed by the values selected for the timing components r t and c t . capacitor c t is charged from the 5.0 v reference through resistor r t to approximately 2.8 v and discharged to 1.2 v by an internal current sink. during the discharge of c t , the oscillator generates an internal blanking pulse that holds the center input of the nor gate high. this causes the output to be in a low state, thus producing a controlled amount of output deadtime. an internal flip ? flop has been incorporated in the ucx844/5 which blanks the output off every other clock cycle by holding one of the inputs of the nor gate high. this in combination with the c t discharge period yields output deadtimes programmable from 50% to 70%. figure 2 shows r t versus oscillator frequency and figure 3, output deadtime versus frequency, both for given values of c t . note that many values of r t and c t will give the same oscillator frequency but only one combination will yield a specific output deadtime at a given frequency. in many noise sensitive applications it may be desirable to frequency ? lock the converter to an external system clock. this can be accomplished by applying a clock signal to the circuit shown in figure 18. for reliable locking, the free ? running oscillator frequency should be set about 10% less than the clock frequency. a method for multi unit synchronization is shown in figure 19. by tailoring the clock waveform, accurate output duty cycle clamping can be achieved to realize output deadtimes of greater than 70%. error amplifier a fully compensated error amplifier with access to the inverting input and output is provided. it features a typical dc voltage gain of 90 db, and a unity gain bandwidth of 1.0 mhz with 57 degrees of phase margin (figure 6). the noninverting input is internally biased at 2.5 v and is not pinned out. the converter output voltage is typically divided down and monitored by the inverting input. the maximum input bias current is ? 2.0 a which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. the error amp output (pin 1) is provide for external loop compensation (figure 29). the output voltage is offset by two diode drops ( 1.4 v) and divided by three before it connects to the inverting input of the current sense comparator. this guarantees that no drive pulses appear at the output (pin 6) when pin 1 is at its lowest state (v ol ). this occurs when the power supply is operating and the load is removed, or at the beginning of a soft ? start interval (figures 21, 22). the error amp minimum feedback resistance is limited by the amplifier?s source current (0.5 ma) and the required output voltage (v oh ) to reach the comparator?s 1.0 v clamp level: r f(min) 3.0 (1.0 v) + 1.4 v 0.5 ma = 8800 current sense comparator and pwm latch the UC3844, uc3845 operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the error amplifier output/compensation (pin 1). thus the error signal controls the inductor current on a cycle ? by ? cycle basis. the current sense comparator pwm latch configuration used ensures that only a single pulse appears at the output during any given oscillator cycle. the inductor current is converted to a voltage by inserting the ground referenced sense resistor r s in series with the source of output switch q1. this voltage is monitored by the current sense input (pin 3) and compared a level derived from the error amp output. the peak inductor current under normal operating conditions is controlled by the voltage at pin 1 where: i pk = v (pin 1) ? 1.4 v 3 r s abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. under these conditions, the current sense comparator threshold will be internally clamped to 1.0 v. therefore the maximum peak switch current is: i pk(max) = 1.0 v r s when designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of r s to a reasonable level. a simple method to adjust this voltage is shown in figure 20. the two external diodes are used to compensate the internal diodes yielding a constant clamp voltage over temperature. erratic operation due to noise pickup can result if there is an excessive reduction of the i pk(max) clamp voltage. a narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. this spike is due to the power transformer interwinding capacitance and output rectifier recovery time. the addition of an rc filter on the current sense input with a time constant that approximates the spike duration will usually eliminate the instability; refer to figure 24.
UC3844, uc3845, uc2844, uc2845 http://onsemi.com 8 + ? sink only positive true logic = r s + internal bias reference regulator oscillator s r q ? v ref uvlo 3.6v 36v v cc 7(12) q1 v in v cc v c 7(11) 6(10) 5(8) 3(5) + 1.0ma error amplifier 1(1) 2(3) 4(7) 8(14) 5(9) gnd output compensation voltage feedback input r t c t v ref ? ? pwm latch current sense comparator r r power ground current sense input 2r r 1.0v pin numbers in parenthesis are for the d suffix soic?14 package. q t + ? + + ? + ? + v cc uvlo output 2.5v figure 16. representative block diagram output/ compensation current sense input latch reset input output capacitor c t latch set input large r t /small c t small r t /large c t figure 17. timing diagram
UC3844, uc3845, uc2844, uc2845 http://onsemi.com 9 undervoltage lockout two undervoltage lockout comparators have been incorporated to guarantee that the ic is fully functional before the output stage is enabled. the positive power supply terminal (v cc and the reference output (v ref ) are each monitored by separate comparators. each has built ? in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. the v cc comparator upper and lower thresholds are 16 v/10 v for the ucx844, and 8.4 v/7.6 v for the ucx845. the v ref comparator upper and lower thresholds are 3.6 v/3/4 v. the large hysteresis and low startup current of the ucx844 makes it ideally suited in off ? line converter applications where efficient bootstrap startup techniques later required (figure 30). the ucx845 is intended for lower voltage dc ? to ? dc converter applications. a 36 v zener is connected as a shunt regulator from v cc to ground. its purpose is to protect the ic from excessive voltage that can occur during system startup. the minimum operating voltage for the ucx844 is 11 v and 8.2 v for the ucx845. output these devices contain a single totem pole output stage that was specifically designed for direct drive of power mosfets. it is capable of up to 1.0 a peak drive current and has a typical rise and fall time of 50 ns with a 1.0 nf load. additional internal circuitry has been added to keep the output in a sinking mode whenever and undervoltage lockout is active. this characteristic eliminates the need for an external pull ? down resistor. the soic ? 14 surface mount package provides separate pins for v c (output supply) and power ground. proper implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. this becomes particularly useful when reducing the i pk(max) clamp level. the separate v c supply input allows the designer added flexibility in tailoring the drive voltage independent of v cc. a zener clamp is typically connected to this input when driving power mosfets in systems where v cc is greater the 20 v. figure 23 shows proper power and control ground connections in a current sensing power mosfet application. reference the 5.0 v bandgap reference is trimmed to 1.0% tolerance at t j = 25 c on the uc284x, and 2.0% on the uc384x. its primary purpose is to supply charging current to the oscillator timing capacitor. the reference has short circuit protection and is capable of providing in excess of 20 ma for powering additional control system circuitry. design considerations do not attempt to construct the converter on wire ? wrap or plug ? in prototype boards. high frequency circuit layout techniques are imperative to prevent pulsewidth jitter. this is usually caused by excessive noise pick ? up imposed on the current sense or v oltage feedback inputs. noise immunity can be improved by lowering circuit impedances at these points. the printed circuit layout should contain a ground plane with low ? current signal and high ? current switch and output grounds returning on separate paths back to the input filter capacitor. ceramic bypass capacitors (0.1 f) connected directly to v cc , v c , and v ref may be required depending upon circuit layout. this provides a low impedance path for filtering the high frequency noise. all high current loops should be kept as short as possible using heavy copper runs to minimize radiated emi. the error amp compensation circuitry and the converter output voltage divider should be located close to the ic and as far as possible from the power switch and other noise generating components. external sync input figure 18. external clock synchronization figure 19. external duty cycle clamp and multi ? unit synchronization the diode clamp is required if the sync amplitude is large enough to cause the bottom side of ct to go more than 300 mv below ground. 47 5(9) r r bias osc v ref r t 8(14) 4(7) 2(3) 1(1) 0.01 c t 2r r ea + ? + 5(9) r r bias osc 8(14) 4(7) 2(3) 1(1) 2r r ea + ? + 7 5.0k 3 8 6 5 1 c r s mc1455 2 r a + ? + ? 4 q 5.0k 5.0k r b to additional ucx84xas f = 1.44 (r a + 2r b )c d max = r b r a + 2r b
UC3844, uc3845, uc2844, uc2845 http://onsemi.com 10 figure 20. adjustable reduction of clamp level figure 21. soft ? start circuit figure 22. adjustable buffered reduction of clamp level with soft ? start figure 23. current sensing power mosfet virtually lossless current sensing can be achieved with the implement of a sensefet power switch. for proper operation during over current conditions, a reduction of the i pk(max) clamp level must be implemented. refer to figures 20 and 22. 5(9) r r bias osc 8(14) 4(7) 2(3) 1(1) 2r r ea + ? + q1 r s 3(5) 5(8) 1.0v ? r s q comp/latch 5.0v ref v clamp v in v cc 7(11) 6(10) ? + + ? + ? + 7(12) + ? r 1 r 2 r 2 v clamp 1.67 + 1 + 0.33 x 10 ?3 i pk(max) v clamp r s where: 0 v clamp 1.0 v r2 r1 1.0ma r 1 r 1 + r 2 5(9) r r bias osc 8(14) 4(7) 2(3) 1(1) 2r r ea + ? + 1.0v ? r s q 5.0v ref ? + + ? + c t soft?start 3600c in f 1.0ma 5(9) r r bias osc 8(14) 4(7) 2(3) 1(1) 2r r ea + ? + q1 r s 3(5) 5(8) 1.0v ? r s q comp/latch 5.0v ref v clamp v in v cc 7(11) 6(10) ? + + ? + ? + 7(12) + ? mpsa63 r1 r2 c t softstart = ? in 1 ? v c r 1 r 2 c r 2 v clamp 1.67 + 1 i pk(max) v clamp r s where: 0 v clamp 1.0 v 1.0ma r 1 3v clamp r 1 + r 2 r s 1/4 w (5) (8) ? r s q comp/latch 5.0v ref v in v cc (11) (10) ? + + ? + ? + (12) + ? power ground to input source return v pin 5 if: sensefet = mtp10n10m r s = 200 then: v pin 5 = 0.075 i pk sensefet r s i pk r ds(on) m g d s k control circuitry ground: to pin (9) r dm(on) + r s + 0.33 x 10 ?3 r 1 r 2 r 1 + r 2 figure 24. current waveform spike suppression the addition of the rc filter will eliminate instability caused by the leading edge spike on the current waveform. q1 r s 3(5) 5(8) ? r s q comp/latch 5.0v ref v in v cc 7(11) 6(10) ? + + ? + ? + 7(12) + ? r c t 1.0m t t t t
UC3844, uc3845, uc2844, uc2845 http://onsemi.com 11 the mcr101 scr must be selected for a holding of less than 0.5 ma at t a(min) . the simple two transistor circuit can be used in place of the scr as shown. all resistors are 10 k. figure 25. mosfet parasitic oscillations figure 26. bipolar transistor drive figure 27. isolated mosfet drive figure 28. latched shutdown figure 29. error amplifier compensation the totem?pole output can furnish negative base current for enhanced transistor turn?off, with the addition of capacitor c 1 . error amp compensation circuit for stabilizing any current?mode topology except for boost and flyback converters operating with continuous inductor current. error amp compensation circuit for stabilizing current?mode boost and flyback topologies operating with continuous inductor current. series gate resistor r g will damp any high frequency parasitic oscillations caused by the mosfet input capacitance and any series wiring inductance in the gate?source circuit. q1 r s 3(5) 5(8) ? r s q comp/latch 5.0v ref v in v cc 7(11) 6(10) ? + + ? + ? + 7(12) + ? r g q1 r s 3(5) 5(8) v in 6(1) c 1 i b + 0 ? base charge removal 8.8 k t
figure 30. 27 watt off ? line flyback regulator t1 ? primary: 45 turns # 26 awg t1 ? secondary 12 v: 9 turns # 30 awg t1 ? (2 strands) bifiliar wound t1 ? secondary 5.0 v: 4 turns (six strands) t1 ? #26 hexfiliar wound t1 ? secondary feedback: 10 turns #30 awg t1 ? (2 strands) bifiliar wound t1 ? core: ferroxcube ec35?3c8 t1 ? bobbin: ferroxcube ec35pcb1 t1 ? gap 0.01" for a primary inductance of 1.0 mh l1 ? 15 h at 5.0 a, coilcraft z7156. l2, l3 ? 25 h at 1.0 a, coilcraft z7157. comp/latch s r q 1n4935 1n4935 5.0v ref bias osc + + 47 100 ea + + 7(12) l1 5.0v/4.0a 2200 1000 + mur110 mbr1635 1000 1000 10 ++ + l2 5.0v rtn 12v/0.3a 1n4937 l3 mur110 12v rtn ?12v/0.3a t1 1.0k 470pf 3(5) 5(8) 6(10) 7(11) 22 1n4937 2.7k 3300pf 4.7k 56k 250 + 115va c 4.7 mda 202 68 5(9) + 1(1) 2(3) 4(7) 33k 0.01 1.0nf 18k 4.7k mtp 4n50 8(14) 10 + + 680pf 0.5 150k 100pf + + + + ? ? ? ? 1n5819 t UC3844, uc3845, uc2844, uc2845 http://onsemi.com 12 test conditions results line regulation: 5.0 v 12 v v in = 95 vac to 130 vac = 50 mv or 0.5% = 24 mv or 0.1% load regulation: 5.0 v 12 v v in = 115 vac, i out = 1.0 a to 4.0 a v in = 115 vac, i out = 100 ma to 300 ma = 300 mv or 3.0% = 60 mv or 0.25% output ripple: 5.0 v 12 v v in = 115 vac 40 mv pp 80 mv pp efficiency v in = 115 vac 70% all outputs are at nominal load currents, unless otherwise noted.
UC3844, uc3845, uc2844, uc2845 http://onsemi.com 13 + ? + internal bias reference regulator oscillator s r q ? v ref uvlo 3.6v 34v 7(12) v in = 15v 7(11) 6(10) 5(8) 3(5) + 0.5ma error amplifier 1(1) 2(3) 4(7) 8(14) 5(9) 10k 1.0nf ? ? pwm latch current sense comparator r r 2r r 1.0v the capacitors equivalent series resistance must limit the drive output current to 1.0 a. an additional series resistor may be required when using tantalum or other low esr capacitors. the converters output can provide excellent line and load regulation by connecting the r2/r1 resistor divider as shown. t + + ? + ? + v cc uvlo 2.5v uc3845 + 47 1n5819 + 15 10 1n5819 connect to pin 2 for closed loop operation. + 47 r2 r1 v o 2 (v in ) v o = 2.5 + 1 r2 r2 output load regulation (open loop configuration) i o (ma) v o (v) 0 2 9 18 36 29.9 28.8 28.3 27.4 24.4 figure 31. step ? up charge pump converter + ? + internal bias reference regulator oscillator s r q ? v ref uvlo 3.6v 34v 7(12) v in = 15v 7(11) 6(10) 5(8) 3(5) + 0.5ma error amplifier 1(1) 2(3) 4(7) 8(14) 5(9) 10k 1.0nf ? ? pwm latch current sense comparator r r 2r r 1.0v the capacitors equivalent series resistance must limit the drive output current to 1.0 a. an additional series resistor may be required when using tantalum or other low esr capacitors. t + + ? + ? + v cc uvlo 2.5v uc3845 + 47 + 15 10 1n5819 + 47 v o ? (v in ) output load regulation i o (ma) v o (v) 0 2 9 18 32 ?14.4 ?13.2 ?12.5 ?11.7 ?10.6 1n5819 figure 32. voltage ? inverting charge pump converter
UC3844, uc3845, uc2844, uc2845 http://onsemi.com 14 ordering information device operating temperature range package shipping ? UC3844d t a = 0 to +70 c soic ? 14 55 units/rail UC3844dg soic ? 14 (pb ? free) 55 units/rail UC3844dr2 soic ? 14 2500 tape & reel UC3844dr2g soic ? 14 (pb ? free) 2500 tape & reel UC3844n pdip ? 8 50 units/rail UC3844ng pdip ? 8 (pb ? free) 50 units/rail uc3845d soic ? 14 55 units/rail uc3845dg soic ? 14 (pb ? free) 55 units/rail uc3845dr2 soic ? 14 2500 tape & reel uc3845dr2g soic ? 14 (pb ? free) 2500 tape & reel uc3845n pdip ? 8 50 units/rail uc3845ng pdip ? 8 (pb ? free) 50 units/rail uc2844d t a = ? 25 to +85 c soic ? 14 55 units/rail uc2844dg soic ? 14 (pb ? free) 55 units/rail uc2844dr2 soic ? 14 2500 tape & reel uc2844dr2g soic ? 14 (pb ? free) 2500 tape & reel uc2844n pdip ? 8 50 units/rail uc2844ng pdip ? 8 (pb ? free) 50 units/rail uc2845d soic ? 14 55 units/rail uc2845dg soic ? 14 (pb ? free) 55 units/rail uc2845dr2 soic ? 14 2500 tape & reel uc2845dr2g soic ? 14 (pb ? free) 2500 tape & reel uc2845n pdip ? 8 50 units/rail uc2845ng pdip ? 8 (pb ? free) 50 units/rail ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. soic ? 14 d suffix case 751a marking diagrams pdip ? 8 n suffix case 626 uc384xn awl yywwg 1 8 uc284xn awl yywwg 1 8 uc384xdg awlyww 1 14 uc284xdg awlyww 1 14 soic ? 8 d1 suffix case 751 x = 4 or 5 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb ? free package 384x alyw 1 8
UC3844, uc3845, uc2844, uc2845 http://onsemi.com 15 package dimensions pdip ? 8 n suffix case 626 ? 05 issue l notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 ? a ? ? b ? ? t ? seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m ??? 10 ??? 10 n 0.76 1.01 0.030 0.040 soic ? 14 d suffix case 751a ? 03 issue g notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. ? a ? ? b ? g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t ? t ? f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019
UC3844, uc3845, uc2844, uc2845 http://onsemi.com 16 package dimensions soic ? 8 d1 suffix case 751 ? 07 issue ag 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 UC3844/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative sensefet is a trademark of semiconductor components industries, llc.

▲Up To Search▲

Price & Availability of UC3844

	To Download UC3844 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .